By Topic

An efficient verifier for finite state machines

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
S. H. Hwang ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; A. R. Newton

The correctness-checking problem of a finite-state machine is considered. The concept of machine cover is revived and used as the basis of the formulation of the verification problem of the design correctness of finite-state machines. The concept of machine cover enables the verifier to efficiently check the sufficiency. The verifier checks to see if the implementation is correct with respect to its specification, which is given as a form of finite-state machine. Since in general the state encoding information is not available for verification purposes, it is assumed that the encoding information is missing. An efficient algorithm for the verification problem is presented along with its implementation. Experimental results show that the approach is promising in terms of speed

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:10 ,  Issue: 3 )