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Novel Design Methodology Using L_{\bf EXT} Sizing in Nanowire CMOS Logic

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6 Author(s)
Kaushal, G. ; Jaypee Inst. of Inf. Technol., Noida, India ; Manhas, S.K. ; Maheshwaram, S. ; Anand, B.
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In this paper, the impact of nanowire source/drain extension, diameter, and channel length on nanowire (NW) device performance is investigated. We present a novel approach using the extension length as tuning parameter to match the drive current of n- and p-FET in NW CMOS logic applicable down to 10-nm gate length. Our approach overcomes the drive matching issue in NW/FinFET based CMOS circuits. We show that, in comparison to conventional CMOS, where the number of NWs/fins in p-FET is used to match n-FET drive, the proposed approach provides a significant reduction in circuit active area and power dissipation. When compared to conventional CMOS inverter, the proposed approach shows 20% lower area, and 35% saving in power in case of NW CMOS inverter. Our results show that extension length tuned-CMOS has an excellent option for low-power applications in both NW and FinFET technologies.

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Nanotechnology, IEEE Transactions on  (Volume:13 ,  Issue: 4 )