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Bit-area efficient embedded pseudo-SRAM utilising dual-threshold hybrid 2T gain cell

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2 Author(s)
Weijie Cheng ; Sch. of Electron. Eng., Kyungpook Nat. Univ., Daegu, South Korea ; Yeonbae Chung

The design and physical implementation of an embedded memory utilising bit-area efficient hybrid gain cell is presented. The memory cells in this work are composed of a high-threshold NMOS write transistor and a standard-threshold NMOS read transistor. The bit data are stored on the parasitic capacitances within the cells. Owing to the combination of low subthreshold-leakage write device and high mobility read device, this NMOS-based hybrid 2T gain cell exhibits much improved data retention and read performance in a compact bit area. The memory arrays operate with a logic-compatible supply voltage; SRAM-like I/O interface; chip-select-controlled 128-row refresh; and non-destructive read with speed comparable with 6T SRAM, but 65% smaller cell area. Measurement results from a 32 kbit pseudo-SRAM test chip implemented in a 130 nm logic CMOS technology demonstrate the effectiveness of the proposed embedded memory techniques.

Published in:

Circuits, Devices & Systems, IET  (Volume:8 ,  Issue: 2 )