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1801-2013  -   Redline Version
IEEE Standard for Design and Verification of Low-Power Integrated Circuits - Redline

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A method is provided for specifying power intent for an electronic design, for use in verification of the structure and behavior of the design in the context of a given power management architecture, and for driving implementation of that power management architecture. The method supports incremental refinement of power intent specifications required for IP-based design flows.