Cart (Loading....) | Create Account
Close category search window
 

Analytical Modeling of Threshold Voltage and Interface Ideality Factor of Nanoscale Ultrathin Body and Buried Oxide SOI MOSFETs With Back Gate Control

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
8 Author(s)
Fasarakis, N. ; Aristotle Univ. of Thessaloniki, Thessaloniki, Greece ; Karatsori, T. ; Tassis, D.H. ; Theodorou, C.G.
more authors

Simple analytical models for the front and back gate threshold voltages and ideality factors with back gate control of lightly doped short channel fully depleted silicon-on-insulator ultrathin body and buried oxide thickness MOSFETs have been developed based on the minimum value of the front and back surface potentials. The threshold voltage and ideality factor models of the front and back gates have been verified with numerical simulations in terms of the device geometry parameters and the applied bias voltages, as well as with experimental results for devices with channel length down to 17 nm. Good agreement between the model, simulation, and experimental results were obtained by calibrating the minimum carrier charge density adequate to achieve the turn-on condition.

Published in:

Electron Devices, IEEE Transactions on  (Volume:61 ,  Issue: 4 )

Date of Publication:

April 2014

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.