By Topic

Compact charge-based 4 bit flash ADC circuit architecture for ANN applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Schmid, A. ; Integrated Syst. Center, Fed. Inst. of Technol., Lausanne, Switzerland ; Leblebici, Y. ; Mlynek, D.

A charge based flash analogue-digital converter (ADC) circuit architecture is presented, which can be used in various artificial neural network (ANN) applications where compactness and high conversion speed are critical. The 4 bit ADC has been realised with an 0.8 μm double-poly process, and tested to confirm its linearity over the full range and a conversion speed of 10 Msamples/s

Published in:

Electronics Letters  (Volume:34 ,  Issue: 8 )