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Negative Bias Temperature Stress Reliability in Trench-Gated P-Channel Power MOSFETs

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6 Author(s)
Andrea Natale Tallarico ; Dept. of Electr., Univ. of Bologna, Cesena, Italy ; Paolo Magnone ; Giacomo Barletta ; Angelo Magrì
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In this paper, we present the results of an experimental analysis of the degradation induced by negative-bias temperature stress (NBTS) in trench-gated p-channel power MOSFETs. Threshold voltage and carrier mobility are affected by hole trapping in bulk oxide and interface-state generation due to oxide electric field effects. A fast recovery phase occurs when gate bias is removed or reduced in order to measure the threshold voltage. Hence, various techniques for evaluating threshold voltage shift are adopted in order to highlight the differences in the dynamics of degradation. We investigate the influence of gate bias levels during the stress. Moreover, with the help of recovery studies, we try to distinguish the impact of interface-state generation and charge trapping on the NBTS degradation.

Published in:

IEEE Transactions on Device and Materials Reliability  (Volume:14 ,  Issue: 2 )