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Multi-cycle tests, with two or more functional clock cycles between scan operations, can be used for test compaction. When tester limitations prevent primary input vectors from being changed at-speed, one of the possible solutions is to hold the primary input vector constant during the functional clock cycles of a multi-cycle test. However, this limits the level of test compaction that can be achieved. To provide an alternative to this solution, a new type of multi-cycle tests has been defined, where the primary input vector is changed during a clock cycle that is applied under a slow clock. This is followed by a run of the same vector applied under a fast clock. Transition faults are activated during the clock cycles that are applied under a fast clock. A test generation procedure that produces such test sets for transition faults has also been described. Experimental results demonstrate that the new type of tests can improve the ability to produce a compact test set for certain benchmark circuits.