Cart (Loading....) | Create Account
Close category search window
 

Top-Down Fabrication of Epitaxial SiGe/Si Multi-(Core/Shell) p-FET Nanowire Transistors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
6 Author(s)
Barraud, S. ; LETI, Commissariat a l'Energie Atomique et aux Energies Alternatives, Grenoble, France ; Hartmann, J.-M. ; Maffini-Alvaro, V. ; Tosti, L.
more authors

Short-gate length epitaxial Si1-xGex/Si multi-(core/shell) p-type nanowire (NW) transistors with high-permittivity dielectric and metal gate were fabricated and their electrical properties examined. Silicon NWs were first of all patterned in ultrathin silicon-on-insulator wafers by lithography and etching. Selective epitaxial growth of Si0.7Ge0.3/Si or Si0.7Ge0.3/Si/Si0.7Ge0.3/Si shells was then performed around the Si NW core. Electrical transport measurements showed a hole mobility improvement up to 100% in Si0.7Ge0.3/Si/Si0.7Ge0.3/Si core/shell NWs (70% in wide planar devices) compared with p-type Si reference field effect transistors (FETs). Finally, a drive current enhancement of 60% compared with reference Si-channel devices was evidenced in multi-(core/shell) p-FET NWs scaled down to 15-nm gate length.

Published in:

Electron Devices, IEEE Transactions on  (Volume:61 ,  Issue: 4 )

Date of Publication:

April 2014

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.