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Profiling of Channel-Hot-Carrier Stress-Induced Trap Distributions Along Channel and Gate Dielectric in High- k Gated MOSFETs by a Modified Charge Pumping Technique

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6 Author(s)
Chun-Chang Lu ; Dept. of Eng. & Syst. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Kuei-Shu Chang-Liao ; Che-Hao Tsao ; Tien-Ko Wang
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To better understand the channel-hot-carrier (CHC)-induced reliability problems, a modified charge-pumping (CP) technique is proposed to characterize the distribution profiles of trap generation in MOSFETs with high- k gate-stack. The effects of gate leakage current on CP measurements were minimized to ensure the correct CP data. While applying dynamic drain bias, the gate-induced drain leakage current is also considered to get correct CP data. Through the CP with dynamic drain bias and various gate pulse frequencies, the profiling of CHC stress-induced interface- and border-traps can be achieved. The CHC stress-induced interface trap generation appears along whole the channel but that-induced border trap generation is mainly located above the pinchoff region near the drain and decreases dramatically toward the center of the channel. Thus, the CHC stress causes quite localized border trap generation at the gate-edge region inside the high- k dielectric. The reliability data measured by CP with different gate voltage swings confirm that CHC stress causes interface trap generation through whole the channel and significant border trap generation at gate-edge region.

Published in:

IEEE Transactions on Electron Devices  (Volume:61 ,  Issue: 4 )