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Four-quadrant analogue CMOS multiplier cell for VLSI signal and information processing

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3 Author(s)
Lau, K.T. ; Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore ; Lee, S.T. ; Ong, V.

A CMOS four-quadrant analogue multiplier cell for VLSI signal and information processing based on a transconductor and associated circuitry to cancel nonidealities is presented. It is designed to operate in the triode region. This multiplier is modular, has a large dynamic input range, high linearity, low power dissipation and can provide either a differential output current or voltage. The design was fabricated using a 1.2 μm CMOS process. Simulation and experimental results are presented and discussed

Published in:

Circuits, Devices and Systems, IEE Proceedings -  (Volume:145 ,  Issue: 2 )

Date of Publication:

Apr 1998

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