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Lateral p-n-p transistors and a complementary bipolar technology have been demonstrated for analog integrated circuits. Besides vertical n-p-n's, this technology provides lateral p-n-p's at the cost of one additional lithographic and dry etching step. Both devices share the same epitaxial layers and feature topside contacts to all terminals. The influence on p-n-p current gain of contact topology (circular versus rectangular), effective base width, base/emitter doping ratio, and temperature was studied in detail. In the range -40°C to 300 °C, the current gain of the p-n-p transistor shows a maximum of ~ 37 around 0 °C and decreases to ~ 8 at 300 °C, whereas in the same range, the gain of n-p-n transistors exhibits a negative temperature coefficient.