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A 160-MHz fourth-order double-sampled SC bandpass sigma-delta modulator

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2 Author(s)
S. Bazarjani ; Qualcomm. Inc., San Diego, CA, USA ; W. M. Snelgrove

A fully differential double-sampled switched-capacitor (SC) architecture for a fourth-order bandpass ΣΔ modulator is presented. This architecture is based on a double-sampled SC delay circuit. The effect of opamp nonidealities (finite dc gain and nonzero input capacitance) on the notch frequency of this modulator is analyzed. The modulator is implemented in a 0.5-μm CMOS technology and operates at a clock frequency of 80 MHz, making the effective sampling rate 160 MHz. The image signal is about 40 dB below the fundamental signal. The measured signal-to-noise-plus-distortion (SNDR) is 47 dB (not including the image) over a 1.25-MHz bandwidth centered at 40 MHz. The circuit operates at 3 V and consumes 65 mW

Published in:

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing  (Volume:45 ,  Issue: 5 )