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Design and implementation of bandpass delta-sigma modulators using half-delay integrators

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5 Author(s)
Chuang, S. ; Dept. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA ; Liu, H. ; Yu, X. ; Sculley, T.L.
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Two bandpass delta-sigma A/D converters using half delay, integrators have been designed and implemented in a 2-μm n-well double-poly double-metal CMOS process. The first design, a fourth-order architecture with an input modulation network, achieves a signal-to-noise ratio (SNR) of 73 dB over a 0.005π input bandwidth, while the second design, a sixth-order topology, yielded a measured SNR of 80 dB over a 0.004π input bandwidth

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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:45 ,  Issue: 5 )