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Compact MOSFET Modeling for Process Variability-Aware VLSI Circuit Design

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1 Author(s)
Saha, S.K. ; Prospicient Devices, Milpitas, CA, USA

This paper presents a systematic methodology to develop compact MOSFET models for process variability-aware VLSI circuit design. Process variability in scaled CMOS technologies severely impacts the functionality, yield, and reliability of advanced integrated circuit devices, circuits, and systems. Therefore, variability-aware circuit design techniques are required for realistic assessment of the impact of random and systematic process variability in advanced VLSI circuit performance. However, variability-aware circuit design requires compact MOSFET variability models for computer analysis of the impact of process variability in VLSI circuit design. This paper describes a generalized methodology to determine the major set of device parameters sensitive to random and systematic process variability in nanoscale MOSFET devices, map each variability-sensitive device parameter to the corresponding compact model parameter of the target compact model, and generate statistical compact MOSFET models for variability-aware VLSI circuit design.

Monte Carlo (MC) simulation data obtained by the generated statistical compact model show the distribution of ON currents for pMOSFETs (IONP) and nMOSFETs (IONN) for local only, global only, and both local and global process variability. The simulated statistical corners along with the nominal (TT) value of drain currents, are, also, superimposed on the plot using solid rectangular symbols. Monte Carlo (MC) simulation data obtained by the generated statistical compact model show the distribution of ON currents for pMOSFETs (IONP) and nMOSFETs (IONN) for local only, global only, and both local and global process variability. The simulated statistical corners along with the nominal (TT) value of drain currents, are, also, superimposed on the plot using solid rectangular symbols.

Published in:

Access, IEEE  (Volume:2 )

Date of Publication:

2014
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