Skip to Main Content
Strain engineering for performance enhancement is an integral part of a state-of-the-art CMOS process flow. However, use of stressors makes the performance of CMOS devices layout dependent. Performance variability arising due to the use of stressor materials is often referred to as Layout Dependent Effect (LDE) variability. The existing delay models do not take LDE into consideration and, therefore, results into unaccounted change in performance and degraded design robustness. In this paper we propose an analytical delay model for Inverter, 2-input NAND and NOR gates while considering LDE variability due to the use of strain engineered devices. We compare our derived model with TCAD calibrated HSPICE simulation results and observe that our model estimates delay well for varying transistor sizes, load capacitances and input signal transition times.