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This 512 kB, 4-way set-associative cache SRAM for a processor is configurable as a 512 k, or larger, second-level cache using one or more cache chips. Speed between the processor and cache in separate packages is achieved by communicating over an independent source-synchronous 72 b data bus. Power is reduced by semi-synchronous design. Supply voltage is 2.5 V and maximum core power is 4.5 W at 450 MHz assuming back-to-back reads. The 0.35 /spl mu/m CMOS process features 4-level metal and a 0.22 /spl mu/m Leff.