By Topic

A 450 MHz 512 kB second-level cache with a 3.6 GB/s data bandwidth

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Bateman, B. ; Intel Corp., Hillsboro, OR, USA ; Freeman, C. ; Halbert, J. ; Hose, K.
more authors

This 512 kB, 4-way set-associative cache SRAM for a processor is configurable as a 512 k, or larger, second-level cache using one or more cache chips. Speed between the processor and cache in separate packages is achieved by communicating over an independent source-synchronous 72 b data bus. Power is reduced by semi-synchronous design. Supply voltage is 2.5 V and maximum core power is 4.5 W at 450 MHz assuming back-to-back reads. The 0.35 /spl mu/m CMOS process features 4-level metal and a 0.22 /spl mu/m Leff.

Published in:

Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International

Date of Conference:

5-7 Feb. 1998