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A chip-to-chip signaling scheme employs partial response detection (PRD) combined with the zero-delay time delivery of a global timing reference, or global mean time (GMT). High-output-impedance drivers and higher termination resistances for signal transmission reduce driver power to the 10 mW range while maintaining a data rate of 500Mb/s. The resulting intersymbol interference (ISI) is eliminated by the PRD receivers, a type of auto-zero-comparator. Signal lines are segmented and pipelined by PRD buffers to limit the segment lengths to below Lmax=cT/2, where c is the effective velocity of signal propagation and T is the bit time. Segmentation reduces the driver power considerably.