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A 640 MB/s bi-directional data strobed, double-data-rate SDRAM with a 40 mW DLL circuit for a 256 MB memory system

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13 Author(s)
Kim, C. ; Samsung Electron. Co. Ltd., Kyungki, South Korea ; Lee, J. ; Lee, J. ; Kim, B.
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In a memory system employing wide channel high-performance DRAMs, skews resulting from nonideal system and chip environments become the most critical factor. This 256 MB memory system achieves 256 Gb/s peak bandwidth with a 160 MHz clock and 64b channel using a /spl plusmn/0.4 V-swing, push-pull type I/O interface (SSTL).

Published in:

Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International

Date of Conference:

5-7 Feb. 1998