Cart (Loading....) | Create Account
Close category search window
 

A CMOS 6b 400 M sample/s ADC with error correction

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Tsukamoto, S. ; Fujitsu VLSI Ltd., Aichi, Japan ; Endo, T. ; Schofield, W.G.

Applications of A/D converters (ADC) in digital data reading, for example hard disk drives (HDD), digital video disk, and 10BaseT, require high speed and low error rate. Short latency is also important for HDD applications that have feedback loops. Most error correction techniques detect at thermometer code zero-to-one transition to reject bubbles (sparkle errors). These techniques require many elements, making high-speed operation difficult in CMOS. This paper describes a CMOS ADC with 2-clock-cycle latency which corrects errors after thermometer code zero-to-one transition detection.

Published in:

Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International

Date of Conference:

5-7 Feb. 1998

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.