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A CMOS 6b 400 M sample/s ADC with error correction

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3 Author(s)
Tsukamoto, S. ; Fujitsu VLSI Ltd., Aichi, Japan ; Endo, T. ; Schofield, W.G.

Applications of A/D converters (ADC) in digital data reading, for example hard disk drives (HDD), digital video disk, and 10BaseT, require high speed and low error rate. Short latency is also important for HDD applications that have feedback loops. Most error correction techniques detect at thermometer code zero-to-one transition to reject bubbles (sparkle errors). These techniques require many elements, making high-speed operation difficult in CMOS. This paper describes a CMOS ADC with 2-clock-cycle latency which corrects errors after thermometer code zero-to-one transition detection.

Published in:

Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International

Date of Conference:

5-7 Feb. 1998

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