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A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator

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12 Author(s)
Yabe, T. ; Toshiba Corp., Kanagawa, Japan ; Miyano, S. ; Sato, K. ; Wada, M.
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This DRAM macro is suitable for a memory generator implementation. The article shows the expandable floor layout scheme (EFLS) of the DRAM macros. A macro architecture that consists of several banks has a disadvantage that the macro size becomes large, because each bank has peripheral circuits for independent operation. The EFLS eliminates this redundancy by sharing the peripheral circuits among the expansion units of the memory array. Two types of floor layouts are supported by EFLS. One is simple I/O type. The other is doubled I/O type. In both of the arrangements, a DRAM macro is formed by combination of 1 Mb memory array segments and peripheral blocks. Each block is manually designed so the macro size is minimized when all the blocks are combined together. Peripheral circuits that can be shared among 1 Mb segments are placed in the peripheral blocks to save the area.

Published in:

Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International

Date of Conference:

5-7 Feb. 1998