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A 100 mm/sup 2/ 0.95 W single-chip MPEG2 MP@ML video encoder with a 128GOPS motion estimator and a multi-tasking RISC-type controller

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19 Author(s)
E. Miyagoshi ; Matsushita Electr. Ind. Co. Ltd., Osaka, Japan ; T. Araki ; T. Sayama ; A. Ohtani
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A single-chip MPEG2 video encoder, VDSP3, has ten cores. All cores are executed in a macroblock-level pipeline similar to that of a previous LSI, VDSP2. The VIF transfers input video data in MPEG format. The ME1 and ME2 functions form a two-step, motion-estimation process. The MSP calculates statistical values for mode selection. The DCTQ performs the forward and inverse functions for both the DCT and quantization. The VLC outputs MPEG2 video streams. The CIF supports both constant-rate and DMA outputs of PES packets. The ERISC controls each core and is capable of performing rate control. The CLKCTL, with a PLL, supplies clock pulses to each core adaptively. The MSP, DCTQ and VLC are modified VDSP2 cores. By using the VDSP3, an MPEG2 MP@ML video encoder system can be realized with two 16 Mb SDRAMs controlled by the MIF in the VDSP3. Regions for the input image, re-ordering, local decoded image and video bit buffer (VBB) are mapped onto the SDRAMs.

Published in:

Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International

Date of Conference:

5-7 Feb. 1998