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Parasitic RC behavior of VLSI interconnects has been the major bottleneck in terms of latency and power consumption of ICs. Recent 3-D ICs promise to reduce the parasitic RC effect by making use of through silicon vias (TSVs). It is therefore essential to extract the RC model of TSVs to assess their promise. Unlike interconnects on metal layers, TSVs exhibit slow-wave and dielectric quasi-transverse-electromagnetic modes due to the coupling to the semiconducting substrate. This TSV behavior can be simulated using analytical methods, 2-D/3-D quasi-static simulators, or 3-D full-wave electromagnetic simulators. This paper describes a methodology to extract parasitic RC models from such simulation data for interconnects in a 3-D IC.