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New techniques for deterministic test pattern generation

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2 Author(s)
Hamzaoglu, I. ; Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA ; Patel, J.H.

This paper presents new techniques for speeding up deterministic test pattern generation for VLSI circuits. These techniques improve the PODEM algorithm by reducing number of backtracks with a low computational cost. This is achieved by finding more necessary signal line assignments, by detecting conflicts earlier, and by avoiding unnecessary work during test generation. We have incorporated these techniques into an ATPG system for combinational circuits, called ATOM. The performance results for the ISCAS85 and full scan version of the ISCAS89 benchmark circuits demonstrated the effectiveness of these techniques on the test generation performance

Published in:

VLSI Test Symposium, 1998. Proceedings. 16th IEEE

Date of Conference:

26-30 Apr 1998

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