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Built-in self testing of sequential circuits using precomputed test sets

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3 Author(s)
Iyengar, V. ; Dept. of Electr. & Comput. Eng., Boston Univ., MA, USA ; Chakrabarty, K. ; Murray, B.T.

We present a new approach to built-in self-test of sequential circuits using precomputed test sets. Our approach is especially suited to circuits containing a large number of flip-flops but few primary inputs. Such circuits are often encountered as embedded cores and filters for digital signal processing, and are inherently difficult to test. We show that statistical encoding of test sets can be combined with low-cost pattern decoding for deterministic BIST. This approach exploits recent advances in sequential circuit ATPG and unlike other BIST schemes, does not require access to gate-level models of the circuit under test. Experimental results show that the proposed method provides higher fault coverage than pseudorandom testing with shorter test application time

Published in:

VLSI Test Symposium, 1998. Proceedings. 16th IEEE

Date of Conference:

26-30 Apr 1998

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