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Estimation of error detection probability and latency of checking methods for a given circuit under check

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1 Author(s)
Kuchukyan, A. ; System Test & Reliability Lab., American Univ. of Armenia, Yerevan, Armenia

A technique of sampling of input vectors (SIV) with statistical measurements is used for the estimation of error detection probability and fault latency of different checking methods. Application of the technique for Berger code, mod3 and parity checking for combinational circuits is considered. The experimental results obtained by a Pilot Software System are presented. The technique may be implemented as an overhead to an already existing fault simulator

Published in:

VLSI Test Symposium, 1998. Proceedings. 16th IEEE

Date of Conference:

26-30 Apr 1998