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Low cost partial scan design: a high level synthesis approach

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4 Author(s)
Flottes, M.L. ; Lab. d''Inf., de Robotique et de Micro-Electron., CNRS, Montpellier, France ; Pires, R. ; Rouzeyre, B. ; Volpe, L.

In this paper, we present a high level synthesis method for partial scan designs. High level testability information are used to guide the synthesis process towards designs with a minimal number of scan registers. The maximal fault coverage is achievable for these designs. This method mainly leans on ad-hoc modifications of the register allocation process

Published in:

VLSI Test Symposium, 1998. Proceedings. 16th IEEE

Date of Conference:

26-30 Apr 1998