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Nonlinear analog DC fault simulation by one-step relaxation

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2 Author(s)
M. W. Tian ; Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA ; C. -J. Richard Shi

Efficient methods have been developed for fault simulation of linear analog circuits. However, DC fault simulation of nonlinear analog circuits-a more practically-relevant problem-remains largely unexplored. In this paper, we propose an one-step relaxation approach to nonlinear DC fault simulation. In this approach, only one Newton-Raphson iteration is performed for the faulty circuit with the DC solution of the good circuit as the initial point, and the results are used to approximate the actual results of exact fault simulation. With one-step relaxation implemented using Householder's formula, the proposed approach is numerically stable, and computationally efficient. It has a very simple circuit interpretation: the nonlinear circuit under test is modeled by a linearized circuit at its operating point, and faults are modeled as faults in the linearized circuit. Experiment results have demonstrated that the proposed approach achieves almost the same fault coverage as exact fault simulation for 29 MCNC Circuit Simulation Workshop benchmark circuits

Published in:

VLSI Test Symposium, 1998. Proceedings. 16th IEEE

Date of Conference:

26-30 Apr 1998