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A simple and efficient method for generating compact IDDQ test set for bridging faults

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2 Author(s)
Shinogi, T. ; Dept. of Electr. & Electron. Eng., Mie Univ., Tsu, Japan ; Hayashi, T.

This paper presents an efficient method for generating a compact test set for IDDQ testing of bridging faults in combinational CMOS circuits. This method is based on the iterative improvement method. Though our method is simple and easy to implement, it is efficient. Experimental results for large ISCAS benchmark circuits demonstrate its efficiency in comparison with results of previous methods

Published in:

VLSI Test Symposium, 1998. Proceedings. 16th IEEE

Date of Conference:

26-30 Apr 1998