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Tin (Sn) for enhancing performance in silicon CMOS

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6 Author(s)
Hussain, A.M. ; Integrated Nanotechnol. Lab., King Abdullah Univ. of Sci. & Technol., Thuwal, Saudi Arabia ; Fahad, H.M. ; Singh, N. ; Torres Sevilla, G.A.
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We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon.

Published in:

Nanotechnology Materials and Devices Conference (NMDC), 2013 IEEE 8th

Date of Conference:

6-9 Oct. 2013