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TSVs (through-silicon vias) can be fabricated by the via-first, via-middle, and via-last from the backside processes. For via-first and via-middle processes, TSVs are formed from the frontside of the wafer which is temporary bonded to a carrier. Then the backside is subjected to backgrinding and Cu revealing such as silicon dry etching, low-temperature isolation SiN/SiO2 deposition, and CMP (chemical-mechanical polishing) to remove the SiN/SiO2 and the Cu and seed/barrier layers of the Cu-filled TSV. On the other hand, for the via-last from the backside process, a carrier is temporary bonded on the frontside of the “finished” wafer (which includes all the metal layers, pads and passivation) and backgrind the backside of the wafer to ≤50 μm thick. TSVs and RDLs (redistribution layers) are formed from the backside of the wafer by the dual-damascene process. There are at least 3 challenges of Cu CMP of TSVs and RDLs fabricated from the backside of a thin wafer, namely (a) the residues in the dies due to the excess of TTV (total thickness variation) resulting from the degassing/deformation of glue during temporary bonding; (b) the residues on wafer edge due to the low down force during CMP to avoid the thin wafer chipping; and (c) Cu residues along the recess areas of the grinding traces during wafer thinning process. In this study, the processes are developed to overcome these three challenges. Specifically, the Cu residues in the dies are reduced substantially by choosing a thermosetting glue over a thermoplastic glue; the edge metal residues are eliminated by the process with a low down force to avoid the chipping of the thin wafer but increasing the time of Cu over-polishing in the high Cu rate slurry and avoiding Cu corrosion; and the Cu residues along the recess areas of grinding traces are resolved by Cu over-polishing using the high passivation Cu slurry to remove the Cu on the recess areas.