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In this paper, two high-speed and low-power I/O circuits are developed using through-silicon-interposer (TSI) for 2.5D integration of multi-core processor and memory in 65 nm CMOS process. For a 3 mm TSI interconnection of transmission line (T-line), the first I/O circuit is a low-voltage-differential-signal (LVDS) buffer and the second one is a current-mode-logic (CML) buffer. To compensate the high-frequency loss from T-line, a pre-emphasis circuit is deployed in the LVDS buffer, and a wide-band inductor-matching is deployed in the CML buffer. Based on the post layout simulation results, the LVDS buffer can achieve 360 mV peak-to-peak differential output signal swing and 563 fs cycle-to-cycle jitter with 10 Gb/s bandwidth and 4.8 mW power consumption. The CML buffer can achieve 240 mV peak-to-peak differential output signal swing and 453 fs jitter with 12.8 Gb/s data-rate and 1.6 mA current consumption under 0.6 V ultra low-power supply.