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Silicon Etch with integrated metrology for through silicon via (TSV) reveal

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5 Author(s)
Laura B. Mauer ; Solid State Equip. LLC, Horsham, PA, USA ; John Taddei ; Elena Lawrence ; Ramey Youssef
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Wet etch is a cost-effective process option to reveal through-silicon vias (TSVs). This paper addresses the methodology for using integrated wafer thickness measurements to provide complete process control.

Published in:

3D Systems Integration Conference (3DIC), 2013 IEEE International

Date of Conference:

2-4 Oct. 2013