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The innovative flip chip assembly process with Non Conductive Film (NCF) contributes to high density and reliable 3D/TSV integrations has been developed and demonstrated. The target package had two tier structure which consisted of a logic device and Wide I/O DRAM. The logic device was fabricated by via-middle process and accompanied with 1200 TSVs, a thickness of 50 μm and 40 μm / 50 μm bump pitch layout. Thermal-compression bonding method with Cu pillar was applied to both connections between the memory die and the logic die and between the logic die and an organic substrate so that the high reliability could be achieved. In this work, NCF laminated on substrates was selected as an underfill material to establish robust process for 3D integrations and to realize the cost effective assembly. As reliability test items, 1500-cycle temperature cycling test, 1000h high temperature storage test, 1000h high humidity test, 500h unbiased highly accelerated stress test and 300h pressure cooker test were performed. Furthermore, 28 nm logic device and Wide I/O DRAM were assembled into the 3D structure with this new technology and 12.8 GB/s transmission and 89 % reduction of I/O power compared to LPDDR3 were demonstrated.