By Topic

Write Scheme Allowing Reduced LRS Nonlinearity Requirement in a 3D-RRAM Array With Selector-Less 1TNR Architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Frederick T. Chen ; Ind. Technol. Res. Inst., Hsinchu, Taiwan ; Yu-Sheng Chen ; Tai-Yuan Wu ; Tzu-Kun Ku

A 3-D resistive random access memory potentially offers lowest cost per bit and highest bit density memory architecture without the use of transistors in the array. However, without the use of selectors attached to each cell in the array, sneak currents are a key concern, causing signal errors, and excess power dissipation. A nonlinear LRS helps to resolve the issue, but to date, reported LRS nonlinearity values are still insufficient. In this letter, we describe how a 1TNR architecture may be designed and operated to take more advantage of the HRS rather than the LRS nonlinearity, allowing sneak currents to be minimized during write operations, without the use of cell selectors. We show how a recently studied TaOx/HfOx device with highly nonlinear ( ~ 105) HRS can be used in block sizes up to 256 Mb without selectors in a 1T8R architecture with a 25% current margin.

Published in:

IEEE Electron Device Letters  (Volume:35 ,  Issue: 2 )