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The robust-algorithm approach to fault tolerance on processor arrays: fault models, fault diameter, and basic algorithms

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2 Author(s)
Parhami, B. ; Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA ; Chi-Hsiang Yeh

With few exceptions, the two issues of algorithm design and fault tolerance for processor arrays have been dealt with separately, in that algorithm developers have assumed the availability of complete fault-free arrays and fault tolerance techniques have aimed at restoring such complete arrays by reconfiguring faulty ones. We present the design of robust algorithms that run efficiently on complete arrays but are also tolerant of fault processors/links in a degraded mode. This is a complementary approach in that our algorithms can be used on reconfigurable arrays that tolerate a certain number of faults while maintaining their regularity, with the graceful degradation feature kicking in once the fault tolerance limit of the reconfiguration scheme is exceeded. The fault models considered in this paper comprise of the faulty processors/links being removed from the pool of resources (removal model) or bypassed in their respective rows/columns (bypass model). We discuss the two models, derive tight upper bounds for the fault diameter of the resulting networks, and present building-block algorithms for semigroup computation, parallel prefix computation, data rearrangement, matrix multiplication and sorting

Published in:

Parallel Processing Symposium, 1998. IPPS/SPDP 1998. Proceedings of the First Merged International ... and Symposium on Parallel and Distributed Processing 1998

Date of Conference:

30 Mar-3 Apr 1998

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