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A carry select adder with conflict free bypass circuit

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2 Author(s)
Shamanna, M. ; University of Idaho ; Whitaker, S.

This paper presents an architecture for a high-speed carry select adder with very long bit lengths utilizing a conflict-free bypass scheme. The proposed scheme has almost half the number of transistors and is faster than a conventional carry select adder. A comparative study is also made between the proposed adder and a Manchester carry chain adder which shows that the proposed scheme has the same transistor count, without suffering any performance degradation, compared to the Manchester carry chain adder.

Published in:

VLSI Design, 1993. Proceedings. The Sixth International Conference on

Date of Conference:

3-6 Jan. 1993