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An 8 bit by 8 bit signed two's complement pipelined multiplier in 1.6μm N well CMOS, capable of throughputs of 230 million multiplications per second, is described. A half bit level pipelined architecture, and the use of true single phase clocked circuitry, are the key features of this design. Simulation studies indicate that the multiplier dissipates 540mW at 230M Hz. The chip complexity is 5176 transistors, and the area is 1.5mm x 1.4mm.
Date of Conference: 3-6 Jan. 1993