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Turbo decoders for modern wireless communication systems have to support high throughput over a wide range of code rates. In order to support the peak throughputs specified by modern standards, parallel turbo-decoding has become a necessity, rendering the corresponding VLSI implementation a highly challenging task. In this paper, we explore the implementation trade-offs of parallel turbo decoders based on sliding-window soft-input soft-output (SISO) maximum a-posteriori (MAP) component decoders. We first introduce a new approach that allows for a systematic throughput comparison between different SISO-decoder architectures, taking their individual trade-offs in terms of window length, error-rate performance and throughput into account. A corresponding analysis of existing architectures clearly shows that the latency of the sliding-window SISO decoders causes diminishing throughput gains with increasing degree of parallelism. In order to alleviate this parallel turbo-decoder predicament, we propose a new SISO-decoder architecture that leads to significant throughput gains and better hardware efficiency compared to existing architectures for the full range of code rates.