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A hybrid power model for RTL power estimation

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5 Author(s)
Yi-Min Jiang ; Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA ; Shi-Yu Huang ; Kwang-Ting Cheng ; D. C. Wang
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We propose a hybrid power model for estimating the power dissipation of a design at the RT-level. This new model combines the advantages of both RT-level and gate-level approaches. We investigate the relationship between steady-state transition power and overall power dissipation. We observe that, statistically, two input sequences causing similar amount of steady-state transitions will exhibit similar overall power dissipation for an RTL module. Based on this observation, we propose a method to construct a hybrid power model for RTL modules. We further propose a hierarchical power estimation method for estimating the power dissipation of data-path consisting of RTL modules. Experimental results show that, for full-chip power estimation, the estimation time of the technique based on our power models is on average 275 times faster than directly running a commercial transistor-level power simulator, and the errors are less than 6% as compared to the transistor-level power simulation results

Published in:

Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific

Date of Conference:

10-13 Feb 1998