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A CMOS smart image sensor LSI for focal-plane compression

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8 Author(s)
Kawahito, S. ; Dept. of Inf. & Comput. Sci., Toyohashi Univ. of Technol., Japan ; Yoshida, M. ; Sasaki, M. ; Miyazaki, D.
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A CMOS smart image sensor LSI with video compression is presented. The proposed on-sensor compression scheme using an analog 2-D DCT processor is particularly useful to achieve low-power one-chip digital camera. A prototype image sensor LSI has been developed using 0.35 μm double polysilicon, triple metal CMOS technology. Image coding using the implemented LSI has been demonstrated

Published in:

Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific

Date of Conference:

10-13 Feb 1998