Logical-physical co-design for deep submicron circuits: challenges and solutions

As IC fabrication capabilities extend down to sub-half-micron, the significance of interconnect delay and power dissipation can no longer be ignored. Existing enhancements to synthesis and physical design tools have not been able to solve the problem. The only remaining alternative is that tradeoffs in logical and physical domains must be addressed in an integrated manner. Vast business opportunities will be lost unless more revolutionary changes to design flow are made. This paper discusses three technologies which are key to performing logic synthesis and physical layout optimization in tandem. They are early floorplanning, layout-driven logic synthesis, and post-layout resynthesis.