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A reduced clock-swing flip-flop (RCSFF) for 63% power reduction

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2 Author(s)
H. Kawaguchi ; Inst. of Ind. Sci., Tokyo Univ., Japan ; T. Sakurai

A reduced clock-swing flip-flop (RCSFF) is proposed, which is composed of a reduced swing clock driver and a special flip-flop which embodies the leakage current cutoff mechanism. The RCSFF can reduce the clock system power of a VLSI down to one-third compared to the conventional flip-flop. This power improvement is achieved through the reduced clock swing down to 1 V. The area and the delay of the RCSFF can also be reduced by a factor of about 20% compared to the conventional flip-flop. The RCSFF can also reduce the RC delay of a long RC interconnect to one-half

Published in:

IEEE Journal of Solid-State Circuits  (Volume:33 ,  Issue: 5 )