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A charge-transfer amplifier and an encoded-bus architecture for low-power SRAM's

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7 Author(s)
S. Kawashima ; Fujitsu Labs. Ltd., Kawasaki, Japan ; T. Mori ; R. Sasagawa ; M. Hamaminato
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This paper proposes and reports a low-power SRAM using a charge-transfer (CT) pre-sense amplifier and a bus signal encoding scheme. The CT amplifier overcomes the Vth relative difference between the pair MOS transistors, and thus reduces the input offset voltage. The encoded-bus scheme reduces the number of signals being switched to cut the capacitive load. These read-path dynamic circuits have eight-timings which a low-power DLL produces. The fabricated 0.35-μm-rule 2k-by-16-bit SRAM operated at 50 MHz with the power dissipation of 5 mW at 1 V

Published in:

IEEE Journal of Solid-State Circuits  (Volume:33 ,  Issue: 5 )