By Topic

A 1 Gbit synchronous dynamic random access memory with an independent subarray-controlled scheme and a hierarchical decoding scheme

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

9 Author(s)
Kyuchan Lee ; DRAM Design, Samsung Electron. Co. Ltd., Kyungki-Do, South Korea ; Changhyun Kim ; Hongil Yoon ; Keum-Yong Kim
more authors

A prototype 1 Gbit synchronous DRAM with independent subarray-controlled isolation and hierarchical decoding schemes is demonstrated to alleviate the difficulties encountered in high-density devices with regard to failure analysis and performance optimization. The scheme to isolate memory arrays from “hard” defects and to overcome the dc leakages of “soft” defects with external sources allows monitoring of the leakage current for the defect analysis and testing of the device without being limited by the capabilities of on-chip voltage sources. A hierarchical decoding scheme with a dynamic CMOS series logic predecoder achieves improvements in circuit speed, power, and complexity. As a result, evaluation of the prototype devices can be facilitated, and the optimized circuit schemes achieve enhanced circuit performance. A fully working 1 Gbit synchronous DRAM with a chip size of 570 mm2 was fabricated using a 0.16 μm CMOS process and tested for excellent functionality up to 143 MHz

Published in:

IEEE Journal of Solid-State Circuits  (Volume:33 ,  Issue: 5 )