By Topic

400-MHz random column operating SDRAM techniques with self-skew compensation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
T. Hamamoto ; ULSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan ; M. Tsukude ; K. Arimoto ; Y. Konishi
more authors

High-speed data transfer is a key factor in future main memory systems. DDR SDRAM (double-data-rate synchronous-DRAM) is one of the candidates for high-speed memory. In this paper we present three techniques to achieve a short access time and high data transfer rate for DDR-SDRAM's. First, a self-skew compensating technique enables 400-Mbit/s address and data detection. Second, a novel trihierarchical WL scheme realizes multibank operation without access or area penalties. Third, an interleaved array access path doubles the array operating frequency and it enables 400-MHz random column operation. A 16-bank 256-Mbit DDR SDRAM circuit has been designed, and the possibility of the realization of random column 200 MHz×32 DDR operation, namely, 1.6-Gbyte/s data rate operation, has been confirmed

Published in:

IEEE Journal of Solid-State Circuits  (Volume:33 ,  Issue: 5 )