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Issue logic for a 600-MHz out-of-order execution microprocessor

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2 Author(s)
Farrell, J.A. ; Digital Equipment Corp., Hudson, MA, USA ; Fischer, Timothy C.

The logic and circuits are presented for a 20-entry instruction queue which scoreboards 80 registers and issues four instructions per cycle in a 600-MHz microprocessor. The request logic and arbiter circuits that control integer execution are described in addition to a novel compaction scheme that maintains temporal order in the queue. The issue logic data path is implemented in 141000 transistors, occupying 10 mm2 in a 0.35-μm CMOS process

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:33 ,  Issue: 5 )