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Nanoelectronics are inherently defect prone, and defect-tolerant logic implementation has emerged as a new foundation to form reliable systems. Crossbar-based architectures have been shown to be promising in future nanoelectronic systems, with most of the existing defect tolerance approaches based on logic mapping. Essentially, mapping-based schemes exploit the freedom of choosing which variables/products (in a logic function) to map to which of the vertical/horizontal wires (in a crossbar). In this paper, we expand the realm of defecting tolerant logic implementation by introducing two approaches orthogonal to mapping-based schemes, namely, logic morphing and fine-grained fine-tuned logic hardening. Logic morphing exploits the various equivalent forms of a logic function to tolerate defects, while calculated logic hardening adds redundancies to make the hardened logic function inherently defect tolerable. A new integrated framework is proposed to utilize the two new schemes while not sacrificing existing mapping-based techniques. The algorithms in the framework can efficiently search for a successful logic implementation in the combined solution space. Simulation results show that the proposed integrated framework boost defect tolerance capability significantly with 2-10 yield improvement, while adding no runtime overhead on top of the basic mapping algorithm.