Cart (Loading....) | Create Account
Close category search window
 

An efficient compiled simulation system for VLIW code verification

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Jae-Woo Ahn ; Dept. of Electr. Eng., Seoul Nat. Univ., South Korea ; Soo-Mook Moon ; Wonyong Sung

We present an efficient compiled simulation system for the verification of a VLIW instruction set architecture and its assembly code. Our existing compiled simulation system is made to be faster by adopting incremental recompilation and C-assembly cosimulation techniques to improve the conventional compiled simulation. As a part of SPARC-based VLIW testbed, the efficiency and validity of our compiled simulation system are verified with three SPEC '89 integer benchmarks and several UNIX utilities

Published in:

Simulation Symposium, 1998. Proceedings. 31st Annual

Date of Conference:

5-9 Apr 1998

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.