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An efficient compiled simulation system for VLIW code verification

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3 Author(s)
Jae-Woo Ahn ; Dept. of Electr. Eng., Seoul Nat. Univ., South Korea ; Soo-Mook Moon ; Wonyong Sung

We present an efficient compiled simulation system for the verification of a VLIW instruction set architecture and its assembly code. Our existing compiled simulation system is made to be faster by adopting incremental recompilation and C-assembly cosimulation techniques to improve the conventional compiled simulation. As a part of SPARC-based VLIW testbed, the efficiency and validity of our compiled simulation system are verified with three SPEC '89 integer benchmarks and several UNIX utilities

Published in:

Simulation Symposium, 1998. Proceedings. 31st Annual

Date of Conference:

5-9 Apr 1998