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A 800 MS/s low power fourth-order continuous-time bandpass ΔΣ modulator (CTBPDSM) with 24 MHz bandwidth at a 200 MHz IF uses a novel power-efficient resonator with a single amplifier as a loopfilter. The single op-amp resonator employs positive feedback to increase the Q-factor. A new fourth-order architecture is introduced for system simplicity and power efficiency. Reducing the number of feedback DACs lowers the power consumption and simplifies the modulator structure. A prototype ADC achieves 58 dB SNDR, 60 dB DR and 65 dB IM3, with a total power consumption of 12 mW. The total die area in 65 nm CMOS is 0.2 mm2.